Printed circuit assemblies (PCA's) are typically tested after manufacture to verify the continuity of traces between pads and vias on the board and to verify that components loaded on the PCA perform within specifications. Such printed circuit assembly testing is generally performed with automated in-circuit testers or ICT's and requires complex tester resources. The tester hardware must generally be capable of probing conductive pads, vias and traces on the board under test.
In-circuit testers (ICT) have traditionally used “bed-of-nails” (BON) access to gain electrical connectivity to circuit wiring (traces, nets, pads) for control and observation capability needed for testing. The Agilent 3070 is one typical in-circuit tester and is available from Agilent Technologies, Inc. of Palo Alto, Calif. This necessitates having access targets within the layout of circuit nets that can be targets for ICT probes. Test access points are usually circular targets with 28 to 35 mil diameter that are connected to traces on the printed circuit board. In some cases these targets are deliberately added test pads, and in other cases the targets are “via” pads surrounding vias already provided in the printed circuit.
Lower diameter targets are increasingly difficult to hit reliably and repeatably, especially when a test fixture may contain several thousand such probes. It is always desirable to use larger diameter targets, but this is in fundamental conflict with the industry trend towards higher densities and smaller geometry devices.
Yet another industry trend is to use higher and higher speed logic families. One Megahertz (MHz) designs became ten MHz designs, then 100 MHz designs, and are now reaching the Gigahertz domain. The increases in logic speed necessitate industry attention to board layout rules for higher-speed interconnects. The goal of these rules is to create a controlled impedance pathway that minimizes noise, crosstalk and signal reflections. Printed circuit boards traces that carry high-speed signals tend to have critical layout requirements and require controlled characteristic impedances. When traditional test probe targets are added, this causes discontinuities in the controlled impedances and may damage signal fidelity.
FIG. 1A illustrates a classic pair of differential transmission signal traces 102a, 102b on a portion of a printed circuit board 100. As illustrated, the printed circuit board 100 is formed as a plurality of layers. In the illustrative embodiment, the printed circuit board 100 includes a ground plane 104 layered over a substrate 105, a dielectric 103 layered over the ground plane 104, traces 102a, 102b layered over the dielectric 103, a solder mask 106 layered exposed surfaces of the dielectric 103, and test access targets 115a and 115b. In such a layout, there are a number of critical parameters that affect the impedance of the signal path. These parameters include trace width 110, trace separation 111, trace thickness 112, and dielectric constants of the solder mask and board material. These parameters influence the inductance, capacitance, and resistance (skin effect and DC) of the traces, which combine to determine the transmission impedance. It is generally desirable to control this value across the entire run of each trace 102a, 102b. 
In some higher speed designs it is also important to control the symmetry of the traces. However, routing signals on a crowded printed circuit board necessitates curves and bends in the path, which makes matching lengths and symmetries more difficult. In some cases, series components (such as series terminations or DC blocking capacitors) may be included in the path, and these have dimensions that differ from the layout parameters. Signals may also have to traverse connectors, which add to the difficulties.
Another trend is toward higher and higher density boards, which are also layout critical. When traditional test probe targets are added to a high-density board, the board layout is generally disturbed, in which adding test probe targets to one or more nodes necessitates moving several others out of the way. Such changes to high-density boards in many cases, may not be practical, as there may not be any room to move traces. If any of the signal traces also happen to be high-frequency signal traces, then the bends needed to re-route them may also have a negative performance impact as well as the negative effects of the conventional target itself.
Additional difficulties arise when testing is considered. Testing requires tester access to circuit traces at particular probe targets. Layout rules typically require test targets to be at least 50 mils apart and may require the diameter of the test point targets to greatly exceed the width of the traces. FIGS. 1A and 1B illustrate test targets 115a, 115b symmetrically positioned 50 mils apart on the differential signal traces 102a, 102b. As seen in FIGS. 1A and 1B, large test targets 115a is being probed by a typical fixture probe 116 with a sharp head 120, such as those available from Interconnect Devices, Inc., 5101 Richland Avenue, Kansas City, Kans. 66106. The sharp probes 116 help break through any oxide or residue build up on the test targets 115a and 115b. 
The positioning of test targets 102a, 102b can be problematic. In many cases the need to keep a minimum separation between targets (typically 50 mils, minimum) is in direct conflict with controlled impedance layout rules. These conflicts lead to either a compromise in controlled impedance integrity and optimal circuit layout for performance and space, or a forced reduction in target placement with a resulting reduction in testability.
While high-speed printed circuit boards are one example of layout-critical circuits, another more general case is that of high-density boards. Adding conventional probe targets to a high-density board will most likely disturb the layout. For example, adding test points to just one or more nodes may require moving several other traces out of the way. In many cases, in a high-density circuit design, this may be impractical, if not impossible, as there may not be any room to move these traces in a crowded circuit layout. If any traces are also high-frequency signal traces, then the re-routing may have an additional negative performance impact as well as the negative effects to the optimal circuit layout itself.
As discussed more fully in U.S. patent application Ser. No. 10/670,649 entitled Printed Circuit Board Test Access Point Structures And Methods For Making The Same filed Sep. 24, 2003 by Kenneth P. Parker et al. and U.S. patent application entitled Method And Apparatus For Manufacturing And Probing Printed Circuit Board Test Access Point Structures filed Oct. 25, 2004 by Kenneth P. Parker and shown in FIGS. 2A–2C, a new paradigm has been developed to replace the old test paradigm where large probe targets are laid out on a printed circuit board and probed with sharp-pointed fixture probes mounted in a test fixture.
As shown in FIGS. 2A–2C small hemi-ellipsoidal solder beads or test access points 18a and 18b are added to traces 12a and 12b on a printed circuit board 10 without perturbing the board's layout or performance by taking advantage of the z-dimension. As illustrated, the printed circuit board 10 is formed as a plurality of layers. In the illustrative embodiment, the printed circuit board 10 includes a ground plane 14 layered over a substrate 15, a dielectric 13 layered over the ground plane 14, traces 12a, 12b layered over the dielectric 13, a solder mask 16 layered exposed surfaces of the traces 12a and 12b and dielectric 13, and test access points 18a and 18b. 
As noted above, an important factor in probing is obtaining a good electrical contact between the fixture probe and the test target. In the old paradigm, this was typically handled by probing with a sharp probe tip 120. However, this method may be problematic with bead probes or test access point structures 18a and 18b, as the test access point structures may have very small dimensions in the x-y plane, in the order of 3–5 mils wide by 15–20 mils long or less. Current design for test guidelines for ICT (in circuit testers) require a minimum 30 mil diameter test pad or target by a chisel or spear tipped probe. The small dimensions of the test access point structures in the x-y plane in combination with the small dimensions of the chisel or spear tipped test fixture probe would very likely create test access accuracy and reliability problems. Simply, it may be hard to hit a small target with a sharp tipped probe with current industry test fixture standards. Also, while a chisel or spear tipped test fixture probe may be effective in disturbing surface contaminants on a 30 mil or greater test pad, assuming it could reliably hit a 3–5 mil test access point structure, it would very likely catastrophically damage the test access point structure. There is a need in the industry for a method to ensure good electrical contact between bead probes or test access point structures and fixture probes.